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[Other] 一个台湾大学生做的MIPS CPU

Description: 一个台湾大学生做MIPS CPU的设计流程，很详细的哦，学计算机组成的同学可以看一下~
Platform: | Size: 918840 | Author: vic_357@126.com | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_creative

Description: 一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
Platform: | Size: 1866752 | Author: 梁文锋 | Hits:

[VHDL-FPGA-Verilog] mlite.tar

Description: Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
Platform: | Size: 100352 | Author: xinyang | Hits:

[OS Develop] ucos2.8-run-mips

Description: UCOS在我的MIPS CPU上的移植 1. 这是UCOS在我的MIPS CPU上的移植代码, 编译工具使用标准的MIPS GCC. 2. 所有CPU相关的代码全在start.S中,相关函数说明如下: -UCOS in my MIPS CPU on one transplant. This is uCOS MIPS CPU in my code the transplant, the compiler uses the standard tools for MIPS GCC.2. All CPU-related code-wide in start.S, the correlation function as follows :
Platform: | Size: 77824 | Author: 许昕 | Hits:

[Windows Develop] MIPS

Description: MIPS模拟器,在windows环境使用,利用Linux下的可执行ELF文件模拟MIPS CPU执行汇编指令.-MIPS simulator use in windows environment, using Linux under the ELF executable file compiled simulation of the implementation of MIPS CPU instructions.
Platform: | Size: 2309120 | Author: RuanYongXiong | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Platform: | Size: 1488896 | Author: kilva | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPStest00

Description: 簡易MIPS CPU程式碼此CPU包含 shift add sub and or stl beq lw sw 等功能-Simple MIPS CPU code for this CPU contains shift add sub and or stl beq lw sw functions
Platform: | Size: 7168 | Author: chen | Hits:

[VHDL-FPGA-Verilog] mipsCPU

Description: MIPS CPU tested in Icarus Verilog
Platform: | Size: 20480 | Author: imromeo | Hits:

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

Description: MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
Platform: | Size: 918528 | Author: 李皓 | Hits:

[Embeded-SCM Develop] mips-cpu

Description: 关于嵌入式的相关资料，主要是讲mips类型的cpu，比较详细-Relevant information on the embedded mainly stresses mips types of cpu, more detailed
Platform: | Size: 287744 | Author: czmxyxbp | Hits:

[Other] cpu

Description: 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
Platform: | Size: 10553344 | Author: gy | Hits:

[VHDL-FPGA-Verilog] CPU

Description: verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
Platform: | Size: 17408 | Author: yk | Hits:

[Windows Develop] mipscpu-source

Description: mips cpu的实现.MIPS是世界上很流行的一种RISC处理器。MIPS公司的R系列就是在此基础上开发的RISC工业产品的微处理器。这些系列产品为很多计算机公司采用构成各种工作站和计算机系统。 -mips cpu implementation. MIPS is the world' s very popular as a RISC processor. MIPS company' s R series is based on the development of industrial products RISC microprocessor. These series of products for many computer companies used to create various workstations and computer systems.
Platform: | Size: 7025664 | Author: 汤龑鸣 | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS

Description: This a verilog code of single cycle mips-This is a verilog code of single cycle mips
Platform: | Size: 587776 | Author: hualin | Hits:

[Linux-Unix] MIPS-CPU-Overview

Description: MIPS CPU概述 MIPS CPU概述-MIPS CPU Overview MIPS CPU Overview MIPS CPU Overview
Platform: | Size: 11264 | Author: zenggang | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] mips-cpu

Description: 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
Platform: | Size: 117760 | Author: 王晓强 | Hits:

[Software Engineering] mips--cpu

Description: 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic design and simulation tests using the Verilog language.
Platform: | Size: 314368 | Author: 朱祖建 | Hits:

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[Other] 一个台湾大学生做的MIPS CPU

[ARM-PowerPC-ColdFire-MIPS] mips_creative

[VHDL-FPGA-Verilog] mlite.tar

[OS Develop] ucos2.8-run-mips

[Windows Develop] MIPS

[VHDL-FPGA-Verilog] CPU

[ARM-PowerPC-ColdFire-MIPS] MIPStest00

[VHDL-FPGA-Verilog] mipsCPU

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

[Embeded-SCM Develop] mips-cpu

[Other] cpu

[VHDL-FPGA-Verilog] CPU

[Windows Develop] mipscpu-source

[Embeded-SCM Develop] mips

[VHDL-FPGA-Verilog] mips

[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS

[Linux-Unix] MIPS-CPU-Overview

[VHDL-FPGA-Verilog] pipelined-mips-cpu

[VHDL-FPGA-Verilog] mips-cpu

[Software Engineering] mips--cpu

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